stm32 /stm32h5 /STM32H533 /TIM1 /TIM1_EGR

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Interpret as TIM1_EGR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UG 0 (B_0x0)CC1G 0 (CC2G)CC2G 0 (CC3G)CC3G 0 (CC4G)CC4G 0 (B_0x0)COMG 0 (B_0x0)TG 0 (B_0x0)BG 0 (B_0x0)B2G

COMG=B_0x0, CC1G=B_0x0, BG=B_0x0, B2G=B_0x0, UG=B_0x0, TG=B_0x0

Description

TIM1 event generation register

Fields

UG

Update generation

0 (B_0x0): No action

1 (B_0x1): Reinitialize the counter and generates an update of the registers.

CC1G

Capture/compare 1 generation

0 (B_0x0): No action

1 (B_0x1): A capture/compare event is generated on channel 1:

CC2G

Capture/compare 2 generation

CC3G

Capture/compare 3 generation

CC4G

Capture/compare 4 generation

COMG

Capture/compare control update generation

0 (B_0x0): No action

1 (B_0x1): CCxE, CCxNE and OCxM bits update (providing CCPC bit is set)

TG

Trigger generation

0 (B_0x0): No action

1 (B_0x1): The TIF flag is set in TIMx_SR register.

BG

Break generation

0 (B_0x0): No action

1 (B_0x1): A break event is generated.

B2G

Break 2 generation

0 (B_0x0): No action

1 (B_0x1): A break 2 event is generated.

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