ETP=B_0x0, SMSPS=B_0x0, ETPS=B_0x0, ETF=B_0x0, TS=B_0x0, OCCS=B_0x0, TS_1=B_0x0, SMS=B_0x0, ECE=B_0x0, SMSPE=B_0x0, SMS_1=B_0x0, MSM=B_0x0
TIM2 slave mode control register
| SMS | SMS[2:0]: Slave mode selection 0 (B_0x0): Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. 1 (B_0x1): Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. 2 (B_0x2): Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. 3 (B_0x3): Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. |
| OCCS | OCREF clear selection 0 (B_0x0): tim_ocref_clr_int is connected to the tim_ocref_clr input 1 (B_0x1): tim_ocref_clr_int is connected to tim_etrf |
| TS | TS[2:0]: Trigger selection 0 (B_0x0): Internal trigger 0 (tim_itr0) 1 (B_0x1): Internal trigger 1 (tim_itr1) 2 (B_0x2): Internal trigger 2 (tim_itr2) 3 (B_0x3): Internal trigger 3 (tim_itr3) 4 (B_0x4): tim_ti1 edge detector (tim_ti1f_ed) 5 (B_0x5): Filtered timer input 1 (tim_ti1fp1) 6 (B_0x6): Filtered timer input 2 (tim_ti2fp2) 7 (B_0x7): External trigger input (tim_etrf) |
| MSM | Master/Slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). |
| ETF | External trigger filter 0 (B_0x0): No filter, sampling is done at fless thansub>DTSless than/sub> 1 (B_0x1): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 2 (B_0x2): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 3 (B_0x3): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 4 (B_0x4): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 5 (B_0x5): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 6 (B_0x6): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 7 (B_0x7): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 8 (B_0x8): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 9 (B_0x9): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 10 (B_0xA): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 11 (B_0xB): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 12 (B_0xC): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 13 (B_0xD): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 14 (B_0xE): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 15 (B_0xF): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 |
| ETPS | External trigger prescaler 0 (B_0x0): Prescaler OFF 1 (B_0x1): tim_etrp frequency divided by 2 2 (B_0x2): tim_etrp frequency divided by 4 3 (B_0x3): tim_etrp frequency divided by 8 |
| ECE | External clock enable 0 (B_0x0): External clock mode 2 disabled 1 (B_0x1): External clock mode 2 enabled. |
| ETP | External trigger polarity 0 (B_0x0): tim_etr_in is non-inverted, active at high level or rising edge 1 (B_0x1): tim_etr_in is inverted, active at low level or falling edge |
| SMS_1 | Slave mode selection When external signals are selected the active edge of the trigger signal (tim_trgi) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if tim_ti1f_ed is selected as the trigger input (TS=00100). Indeed, tim_ti1f_ed outputs 1 pulse for each transition on tim_ti1f, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the tim_trgo signal must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal clock. 1 (B_0x1): Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. |
| TS_1 | Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for product specific implementation details. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal trigger 0 (tim_itr0) 1 (B_0x1): Internal trigger 1 (tim_itr1) 2 (B_0x2): Internal trigger 2 (tim_itr2) 3 (B_0x3): Internal trigger 3 (tim_itr3) |
| SMSPE | SMS preload enable 0 (B_0x0): SMS[3:0] bitfield is not preloaded 1 (B_0x1): SMS[3:0] preload is enabled |
| SMSPS | SMS preload source 0 (B_0x0): The transfer is triggered by the Timer’s Update event 1 (B_0x1): The transfer is triggered by the Index event |