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stm32 /stm32h5 /STM32H533 /VREFBUF /VREFBUF_CSR

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Interpret as VREFBUF_CSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ENVR 0 (B_0x0)HIZ 0 (B_0x0)VRR 0VRS

HIZ=B_0x0, VRR=B_0x0, ENVR=B_0x0

Description

VREFBUF control and status register

Fields

ENVR

Voltage reference buffer mode enable

0 (B_0x0): Internal voltage reference mode disable (external voltage reference mode).

1 (B_0x1): Internal voltage reference mode (reference buffer enable or hold mode) enable.
HIZ

High impedance mode

0 (B_0x0): Vless thansub>REF+less than/sub> pin is internally connected to the voltage reference buffer output.

1 (B_0x1): Vless thansub>REF+less than/sub> pin is high impedance.
VRR

Voltage reference buffer ready

0 (B_0x0): the voltage reference buffer output is not ready.

1 (B_0x1): the voltage reference buffer output reached the requested level.
VRS

Voltage reference scale

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32