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stm32 /stm32h5 /STM32H562 /ADC1 /ADC_SQR1

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Interpret as ADC_SQR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)L0SQ10SQ20SQ30SQ4

L=B_0x0

Description

ADC regular sequence register 1

Fields

L

Regular channel sequence length

0 (B_0x0): 1 conversion

1 (B_0x1): 2 conversions

15 (B_0xF): 16 conversions
SQ1

1st conversion in regular sequence
SQ2

2nd conversion in regular sequence
SQ3

3rd conversion in regular sequence
SQ4

4th conversion in regular sequence

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32