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stm32 /stm32h5 /STM32H562 /SPI1 /SPI_IFCR

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Interpret as SPI_IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOTC)EOTC 0 (TXTFC)TXTFC 0 (UDRC)UDRC 0 (OVRC)OVRC 0 (CRCEC)CRCEC 0 (TIFREC)TIFREC 0 (MODFC)MODFC 0 (SUSPC)SUSPC

Description

SPI/I2S interrupt/status flags clear register

Fields

EOTC

end of transfer flag clear Writing a 1 into this bit clears EOT flag in the SPI_SR register
TXTFC

transmission transfer filled flag clear Writing a 1 into this bit clears TXTF flag in the SPI_SR register
UDRC

underrun flag clear Writing a 1 into this bit clears UDR flag in the SPI_SR register
OVRC

overrun flag clear Writing a 1 into this bit clears OVR flag in the SPI_SR register
CRCEC

CRC error flag clear Writing a 1 into this bit clears CRCE flag in the SPI_SR register
TIFREC

TI frame format error flag clear Writing a 1 into this bit clears TIFRE flag in the SPI_SR register
MODFC

mode fault flag clear Writing a 1 into this bit clears MODF flag in the SPI_SR register
SUSPC

SUSPend flag clear Writing a 1 into this bit clears SUSP flag in the SPI_SR register

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32