SYNCMISS=B_0x0, TRIMOVF=B_0x0, SYNCOKF=B_0x0, ESYNCF=B_0x0, SYNCERR=B_0x0, FEDIR=B_0x0, ERRF=B_0x0, SYNCWARNF=B_0x0
CRS interrupt and status register
| SYNCOKF | SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 (B_0x0): No SYNC event OK signalized 1 (B_0x1): SYNC event OK signalized |
| SYNCWARNF | SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 0 (B_0x0): No SYNC warning signalized 1 (B_0x1): SYNC warning signalized |
| ERRF | Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 0 (B_0x0): No synchronization or trimming error signalized 1 (B_0x1): Synchronization or trimming error signalized |
| ESYNCF | Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 0 (B_0x0): No expected SYNC signalized 1 (B_0x1): Expected SYNC signalized |
| SYNCERR | SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action has to be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0 (B_0x0): No SYNC error signalized 1 (B_0x1): SYNC error signalized |
| SYNCMISS | SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0 (B_0x0): No SYNC missed error signalized 1 (B_0x1): SYNC missed error signalized |
| TRIMOVF | Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0 (B_0x0): No trimming error signalized 1 (B_0x1): Trimming error signalized |
| FEDIR | Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 0 (B_0x0): Upcounting direction, the actual frequency is above the target. 1 (B_0x1): Downcounting direction, the actual frequency is below the target. |
| FECAP | Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to for more details about FECAP usage. |