FRAME_RIS=B_0x0, ERR_RIS=B_0x0, OVR_RIS=B_0x0
DCMI raw interrupt status register
| FRAME_RIS | Capture complete raw interrupt status This bit is set when a frame or window has been captured. In case of a cropped window, this bit is set at the end of line of the last line in the crop. It is set even if the captured frame is empty (e.g. window cropped outside the frame). The bit is cleared by setting the FRAME_ISC bit of the DCMI_ICR register. 0 (B_0x0): No new capture 1 (B_0x1): A frame has been captured. |
| OVR_RIS | Overrun raw interrupt status The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register. 0 (B_0x0): No data buffer overrun occurred 1 (B_0x1): A data buffer overrun occurred and the data FIFO is corrupted. |
| ERR_RIS | Synchronization error raw interrupt status This bit is valid only in the embedded synchronization mode. It is cleared by setting the ERR_ISC bit of the DCMI_ICR register. Note: This bit is available only in embedded synchronization mode. 0 (B_0x0): No synchronization error detected 1 (B_0x1): Embedded synchronization characters are not received in the correct order. |
| VSYNC_RIS | DCMI_VSYNC raw interrupt status This bit is set when the DCMI_VSYNC signal changes from the inactive state to the active state. In the case of embedded synchronization, this bit is set only if the CAPTURE bit is set in DCMI_CR. It is cleared by setting the VSYNC_ISC bit of the DCMI_ICR register. |
| LINE_RIS | Line raw interrupt status This bit gets set when the DCMI_HSYNC signal changes from the inactive state to the active state. It goes high even if the line is not valid. In the case of embedded synchronization, this bit is set only if the CAPTURE bit in DCMI_CR is set. It is cleared by setting the LINE_ISC bit of the DCMI_ICR register. |