HSREF_CLK_DIV=B_0x0, TS1_START=B_0x0, REFCLK_SEL=B_0x0, Q_MEAS_OPT=B_0x0, TS1_EN=B_0x0
Temperature sensor configuration register 1
| TS1_EN | Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready. 0 (B_0x0): Temperature sensor 1 disabled 1 (B_0x1): Temperature sensor 1 enabled |
| TS1_START | Start frequency measurement on temperature sensor 1 This bit is set and cleared by software. 0 (B_0x0): No software trigger. 1 (B_0x1): Software trigger for a frequency measurement. (only if TS1 is ready). |
| TS1_INTRIG_SEL | Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input. |
| TS1_SMP_TIME | Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE. |
| REFCLK_SEL | Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE). 0 (B_0x0): High speed reference clock (PCLK) 1 (B_0x1): Low speed reference clock (LSE) |
| Q_MEAS_OPT | Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1). 0 (B_0x0): Measurement with calibration 1 (B_0x1): Measurement without calibration |
| HSREF_CLK_DIV | High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). … 0 (B_0x0): No divider 1 (B_0x1): No divider 2 (B_0x2): 1/2 division ratio 127 (B_0x7F): 1/127 division ratio |