TPS0=B_0x0, RPS0=B_0x0
Debug status register
| AXWHSTS | AHB Master Write Channel When high, this bit indicates that the write channel of the AHB master FMSs are in non-idle state. |
| RPS0 | DMA Channel Receive Process State This field indicates the Rx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 0 (B_0x0): Stopped (Reset or Stop Receive Command issued) 1 (B_0x1): Running (Fetching Rx Transfer Descriptor) 2 (B_0x2): Reserved for future use 3 (B_0x3): Running (Waiting for Rx packet) 4 (B_0x4): Suspended (Rx Descriptor Unavailable) 5 (B_0x5): Running (Closing the Rx Descriptor) 6 (B_0x6): Timestamp write state 7 (B_0x7): Running (Transferring the received packet data from the Rx buffer to the system memory) |
| TPS0 | DMA Channel Transmit Process State This field indicates the Tx DMA FSM state for Channel: The MSB of this field always returns 0. This field does not generate an interrupt. 0 (B_0x0): Stopped (Reset or Stop Transmit Command issued) 1 (B_0x1): Running (Fetching Tx Transfer Descriptor) 2 (B_0x2): Running (Waiting for status) 3 (B_0x3): Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) 4 (B_0x4): Timestamp write state 5 (B_0x5): Reserved for future use 6 (B_0x6): Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) 7 (B_0x7): Running (Closing Tx Descriptor) |