stm32 /stm32h5 /STM32H563 /ETH /ETH_MTLRXQDR

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Interpret as ETH_MTLRXQDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RWCSTS)RWCSTS 0 (B_0x0)RRCSTS 0 (B_0x0)RXQSTS 0PRXQ

RRCSTS=B_0x0, RXQSTS=B_0x0

Description

Rx queue debug register

Fields

RWCSTS

MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL Rx queue Write controller is active, and it is transferring a received packet to the Rx queue.

RRCSTS

MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:

0 (B_0x0): Idle state

1 (B_0x1): Reading packet data

2 (B_0x2): Reading packet status (or timestamp)

3 (B_0x3): Flushing the packet data and status

RXQSTS

MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx queue:

0 (B_0x0): Rx queue empty

1 (B_0x1): Rx queue fill-level below flow-control deactivate threshold

2 (B_0x2): Rx queue fill-level above flow-control activate threshold

3 (B_0x3): Rx queue full

PRXQ

Number of Packets in Receive Queue This field indicates the current number of packets in the Rx queue. The theoretical maximum value for this field is 256Kbyte/16bytes = 16K Packets, that is, Max_Queue_Size/Min_Packet_Size.

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