stm32 /stm32h5 /STM32H563 /EXTI /EXTI_RTSR2

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Interpret as EXTI_RTSR2

RT50=B_0x0, RT53=B_0x0, RT46=B_0x0

Description

EXTI rising trigger selection register 2

Fields

RT46	Rising trigger event configuration bit of configurable event input xsup (1)/sup When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 0 (B_0x0): Rising trigger disabled (for event and interrupt) for input line 1 (B_0x1): Rising trigger enabled (for event and interrupt) for input line
RT50	Rising trigger event configuration bit of configurable event input xsup (1)/sup When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 0 (B_0x0): Rising trigger disabled (for event and interrupt) for input line 1 (B_0x1): Rising trigger enabled (for event and interrupt) for input line
RT53	Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. 0 (B_0x0): Rising trigger disabled (for event and interrupt) for input line 1 (B_0x1): Rising trigger enabled (for event and interrupt) for input line

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