stm32 /stm32h5 /STM32H563 /FLASH /FLASH_OPTSR2_CUR

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Interpret as FLASH_OPTSR2_CUR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SRAM13_RST 0 (B_0x0)SRAM2_RST 0 (B_0x0)BKPRAM_ECC 0 (B_0x0)SRAM3_ECC 0 (B_0x0)SRAM2_ECC 0 (B_0x0)USBPD_DIS 0TZEN

USBPD_DIS=B_0x0, BKPRAM_ECC=B_0x0, SRAM2_ECC=B_0x0, SRAM2_RST=B_0x0, SRAM13_RST=B_0x0, SRAM3_ECC=B_0x0

Description

FLASH option status register 2

Fields

SRAM13_RST

SRAM1 and SRAM3 erase upon system reset

0 (B_0x0): SRAM1 and SRAM3 erased when a system reset occurs

1 (B_0x1): SRAM1 and SRAM3 not erased when a system reset occurs

SRAM2_RST

SRAM2 erase when system reset

0 (B_0x0): SRAM2 erased when a system reset occurs

1 (B_0x1): SRAM2 not erased when a system reset occurs.

BKPRAM_ECC

Backup RAM ECC detection and correction disable

0 (B_0x0): BKPRAM ECC check enabled

1 (B_0x1): BKPRAM ECC check disabled

SRAM3_ECC

SRAM3 ECC detection and correction disable

0 (B_0x0): SRAM3 ECC check enabled

1 (B_0x1): SRAM3 ECC check disabled

SRAM2_ECC

SRAM2 ECC detection and correction disable

0 (B_0x0): SRAM2 ECC check enabled

1 (B_0x1): SRAM2 ECC check disabled

USBPD_DIS

USB power delivery configuration option bit

0 (B_0x0): Enabled

1 (B_0x1): Disabled

TZEN

TrustZone enable configuration bits This bit enables the device is in TrustZone mode during an option byte change.

180 (B_0xB4): TrustZone enabled.

195 (B_0xC3): TrustZone disabled

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