PGSERR=B_0x0, WRPERR=B_0x0, INCERR=B_0x0, DBNE=B_0x0, EOP=B_0x0, OBKERR=B_0x0, STRBERR=B_0x0, BSY=B_0x0, WBNE=B_0x0, OBKWERR=B_0x0
FLASH secure status register
| BSY | busy flag BSY flag indicates that a FLASH memory is busy (write, erase, option byte change, OBK operations). It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs. 0 (B_0x0): no programming, erase or option byte change operation being executed 1 (B_0x1): programming, erase or option byte change operation being executed |
| WBNE | write buffer not empty flag WBNE flag is set when the flash interface is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW bit in FLASH_SECCR the flash interface detects an error that involves data loss This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data. 0 (B_0x0): write buffer empty or full 1 (B_0x1): write buffer waiting data to complete |
| DBNE | data buffer not empty flag DBNE flag is set when the embedded flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free. 0 (B_0x0): data buffer not used 1 (B_0x1): data buffer used, wait |
| EOP | end of operation flag EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register. 0 (B_0x0): no operation completed 1 (B_0x1): a operation completed |
| WRPERR | write protection error flag WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR. 0 (B_0x0): no write protection error occurred 1 (B_0x1): a write protection error occurred |
| PGSERR | programming sequence error flag PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR. 0 (B_0x0): no sequence error occurred 1 (B_0x1): a sequence error occurred |
| STRBERR | strobe error flag STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR. 0 (B_0x0): no strobe error occurred 1 (B_0x1): a strobe error occurred |
| INCERR | inconsistency error flag INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR. 0 (B_0x0): no inconsistency error occurred 1 (B_0x1): a inconsistency error occurred |
| OBKERR | OBK general error flag OBKERR flag is raised when the OBK-HDPL signal from the SBS does not match the HDPL value associated with the key slot during access to the key location. Alternatively also when the ALT_SECT is unexpectedly changed while the write buffer is being filled. 0 (B_0x0): no OBK general error occurred 1 (B_0x1): an OBK general error occurred |
| OBKWERR | OBK write error flag OBKWERR flag is raised when the address is not virgin on a write access to the OBK storage. Alternatively also when the OBK selector in the alternate sector is not virgin during a swap operation. 0 (B_0x0): no OBK write error occurred 1 (B_0x1): an OBK write error occurred |