WIEN=B_0x0, UNFLIEN=B_0x0, RESET=B_0x0, OVFLIEN=B_0x0, SATIEN=B_0x0, DMAREN=B_0x0, DMAWEN=B_0x0, RIEN=B_0x0, CLIPEN=B_0x0
FMAC control register
| RIEN | Enable read interrupt This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No read interrupt requests are generated. 1 (B_0x1): Enabled. An interrupt request is generated while the Y buffer EMPTY flag is not set. |
| WIEN | Enable write interrupt This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No write interrupt requests are generated. 1 (B_0x1): Enabled. An interrupt request is generated while the X1 buffer FULL flag is not set. |
| OVFLIEN | Enable overflow error interrupts This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No interrupts are generated upon overflow detection. 1 (B_0x1): Enabled. An interrupt request is generated if the OVFL flag is set |
| UNFLIEN | Enable underflow error interrupts This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No interrupts are generated upon underflow detection. 1 (B_0x1): Enabled. An interrupt request is generated if the UNFL flag is set |
| SATIEN | Enable saturation error interrupts This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No interrupts are generated upon saturation detection. 1 (B_0x1): Enabled. An interrupt request is generated if the SAT flag is set |
| DMAREN | Enable DMA read channel requests This bit can only be modified when START= 0 in the FMAC_PARAM register. A read returns the current state of the bit. 0 (B_0x0): Disable. No DMA requests are generated 1 (B_0x1): Enable. DMA requests are generated while the Y buffer is not empty. |
| DMAWEN | Enable DMA write channel requests This bit can only be modified when START= 0 in the FMAC_PARAM register. A read returns the current state of the bit. 0 (B_0x0): Disable. No DMA requests are generated 1 (B_0x1): Enable. DMA requests are generated while the X1 buffer is not full. |
| CLIPEN | Enable clipping 0 (B_0x0): Clipping disabled. Values at the output of the accumulator which exceed the q1.15 range, wrap. 1 (B_0x1): Clipping enabled. Values at the output of the accumulator which exceed the q1.15 range are saturated to the maximum positive or negative value (+1 or -1) according to the sign. |
| RESET | Reset FMAC unit This resets the write and read pointers, the internal control logic, the FMAC_SR register and the FMAC_PARAM register, including the START bit if active. Other register settings are not affected. This bit is reset by hardware. 0 (B_0x0): Reset inactive 1 (B_0x1): Reset active |