ATTHIZ=B_0x0, ATTSET=B_0x0
Attribute memory space timing register
| ATTSET | Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles 255 (B_0xFF): reserved. |
| ATTWAIT | Attribute memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 1 (B_0x1): 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) 254 (B_0xFE): 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 255 (B_0xFF): reserved. |
| ATTHOLD | Attribute memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: 1 (B_0x1): 1 HCLK cycle for write access / 3 HCLK cycles for read access 254 (B_0xFE): 254 HCLK cycles for write access / 256 HCLK cycles for read access 255 (B_0xFF): reserved. |
| ATTHIZ | Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0 (B_0x0): 0 HCLK cycle 254 (B_0xFE): 255 HCLK cycles 255 (B_0xFF): reserved. |