TAR=B_0x0, ECCEN=B_0x0, PTYP=B_0x0, TCLR=B_0x0, PBKEN=B_0x0, PWAITEN=B_0x0, ECCPS=B_0x0, TAR3=B_0x0, PWID=B_0x0
NAND Flash control registers
PWAITEN | Wait feature enable bit Enables the Wait feature for the NAND Flash memory bank: 0 (B_0x0): disabled 1 (B_0x1): enabled |
PBKEN | NAND Flash memory bank enable bit Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus 0 (B_0x0): Corresponding memory bank is disabled (default after reset) 1 (B_0x1): Corresponding memory bank is enabled |
PTYP | Memory type Defines the type of device attached to the corresponding memory bank: 0 (B_0x0): Reserved, must be kept at reset value 1 (B_0x1): NAND Flash (default after reset) |
PWID | Data bus width Defines the external memory device width. 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits (default after reset). 2 (B_0x2): reserved. 3 (B_0x3): reserved. |
ECCEN | ECC computation logic enable bit 0 (B_0x0): ECC logic is disabled and reset (default after reset), 1 (B_0x1): ECC logic is enabled. |
TCLR | CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 HCLK cycle (default) 15 (B_0xF): 16 HCLK cycles |
TAR | ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 HCLK cycle (default) |
TAR3 | ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). Time is: t_ar = (TAR + SET + 2) THCLK where THCLK is the HCLK clock period Note: SET is MEMSET or ATTSET according to the addressed space. 0 (B_0x0): 1 HCLK cycle (default) |
ECCPS | ECC page size Defines the page size for the extended ECC: 0 (B_0x0): 256 bytes 1 (B_0x1): 512 bytes 2 (B_0x2): 1024 bytes 3 (B_0x3): 2048 bytes 4 (B_0x4): 4096 bytes 5 (B_0x5): 8192 bytes |