CNTB2EN=B_0x0, CNTB4EN=B_0x0, CNTB3EN=B_0x0, CNTB1EN=B_0x0
PSRAM chip select counter register
| CSCOUNT | Chip select counter. These bits are written by software to define the maximum chip select low pulse duration. It is expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses. The counter is disabled if the programmed value is 0. |
| CNTB1EN | Counter Bank 1 enable This bit enables the chip select counter for PSRAM/NOR Bank 1. 0 (B_0x0): Counter disabled for Bank 1 1 (B_0x1): Counter enabled for Bank 1 |
| CNTB2EN | Counter Bank 2 enable This bit enables the chip select counter for PSRAM/NOR Bank 2. 0 (B_0x0): Counter disabled for Bank 2 1 (B_0x1): Counter enabled for Bank 2 |
| CNTB3EN | Counter Bank 3 enable This bit enables the chip select counter for PSRAM/NOR Bank 3. 0 (B_0x0): Counter disabled for Bank 3. 1 (B_0x1): Counter enabled for Bank 3 |
| CNTB4EN | Counter Bank 4 enable This bit enables the chip select counter for PSRAM/NOR Bank 4. 0 (B_0x0): Counter disabled for Bank 4 1 (B_0x1): Counter enabled for Bank 4 |