MEMHOLD=B_0x0, MEMSET=B_0x0, MEMHIZ=B_0x0
Common memory space timing register
| MEMSET | Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles |
| MEMWAIT | Common memory wait time Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space on socket. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK: 1 (B_0x1): 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 254 (B_0xFE): 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) 255 (B_0xFF): reserved. |
| MEMHOLD | Common memory hold time Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: 0 (B_0x0): reserved. 1 (B_0x1): 1 HCLK cycle for write access / 3 HCLK cycles for read access 254 (B_0xFE): 254 HCLK cycles for write access / 256 HCLK cycles for read access 255 (B_0xFF): reserved. |
| MEMHIZ | Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0 (B_0x0): 1 HCLK cycle 254 (B_0xFE): 255 HCLK cycles 255 (B_0xFF): reserved. |