RPIPE=B_0x0, NR=B_0x0, RBURST=B_0x0, MWID=B_0x0, NB=B_0x0, CAS=B_0x0, WP=B_0x0, NC=B_0x0, SDCLK=B_0x0
SDRAM control registers 1
| NC | Number of column address bits These bits define the number of bits of a column address. 0 (B_0x0): 8 bits 1 (B_0x1): 9 bits 2 (B_0x2): 10 bits 3 (B_0x3): 11 bits. |
| NR | Number of row address bits These bits define the number of bits of a row address. 0 (B_0x0): 11 bit 1 (B_0x1): 12 bits 2 (B_0x2): 13 bits 3 (B_0x3): reserved. |
| MWID | Memory data bus width. These bits define the memory device width. 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits 3 (B_0x3): reserved. |
| NB | Number of internal banks This bit sets the number of internal banks. 0 (B_0x0): Two internal Banks 1 (B_0x1): Four internal Banks |
| CAS | CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles 0 (B_0x0): reserved. 1 (B_0x1): 1 cycle 2 (B_0x2): 2 cycles 3 (B_0x3): 3 cycles |
| WP | Write protection This bit enables write mode access to the SDRAM bank. 0 (B_0x0): Write accesses allowed 1 (B_0x1): Write accesses ignored |
| SDCLK | SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care. 0 (B_0x0): SDCLK clock disabled 2 (B_0x2): SDCLK period = 2 x HCLK periods 3 (B_0x3): SDCLK period = 3 x HCLK periods |
| RBURST | Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care. 0 (B_0x0): single read requests are not managed as bursts 1 (B_0x1): single read requests are always managed as bursts |
| RPIPE | Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only. 0 (B_0x0): No clock cycle delay 1 (B_0x1): One clock cycle delay 2 (B_0x2): Two clock cycle delay 3 (B_0x3): reserved. |