ILS=B_0x0, FEMPT=B_0x0, IREN=B_0x0, IFS=B_0x0, IRS=B_0x0, ILEN=B_0x0, IFEN=B_0x0
FIFO status and interrupt register
| IRS | Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. 0 (B_0x0): No interrupt rising edge occurred 1 (B_0x1): Interrupt rising edge occurred |
| ILS | Interrupt high-level status The flag is set by hardware and reset by software. 0 (B_0x0): No Interrupt high-level occurred 1 (B_0x1): Interrupt high-level occurred |
| IFS | Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it is set. 0 (B_0x0): No interrupt falling edge occurred 1 (B_0x1): Interrupt falling edge occurred |
| IREN | Interrupt rising edge detection enable bit 0 (B_0x0): Interrupt rising edge detection request disabled 1 (B_0x1): Interrupt rising edge detection request enabled |
| ILEN | Interrupt high-level detection enable bit 0 (B_0x0): Interrupt high-level detection request disabled 1 (B_0x1): Interrupt high-level detection request enabled |
| IFEN | Interrupt falling edge detection enable bit 0 (B_0x0): Interrupt falling edge detection request disabled 1 (B_0x1): Interrupt falling edge detection request enabled |
| FEMPT | FIFO empty Read-only bit that provides the status of the FIFO 0 (B_0x0): FIFO not empty 1 (B_0x1): FIFO empty |