MIS0=B_0x0, MIS4=B_0x0, MIS2=B_0x0, MIS5=B_0x0, MIS3=B_0x0, MIS1=B_0x0, MIS6=B_0x0, MIS7=B_0x0
GPDMA secure masked interrupt status register
| MIS0 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS1 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS2 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS3 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS4 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS5 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS6 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |
| MIS7 | masked interrupt status of the secure channel x (x = 7 to 0) 0 (B_0x0): no interrupt occurred on the secure channel x 1 (B_0x1): an interrupt occurred on the secure channel x |