INVSECSTATE=B_0x0, SRWILADIS=B_0x0, GLOCK=B_0x0
GTZC1 SRAM1 MPCBB control register
| GLOCK | lock the control register of the MPCBB until next reset This bit is cleared by default and once set, it can not be reset until system reset. 0 (B_0x0): control register not locked 1 (B_0x1): control register locked |
| INVSECSTATE | SRAMx clocks security state This bit is used to define the internal SRAMs clocks control in RCC as secure or not. 0 (B_0x0): SRAMs clocks are secure if a secure area exists in the MPCBB. It is non secure if there is no secure area. 1 (B_0x1): SRAMs clocks are non-secure even if a secure area exists in the MPCBB, and secure even if no secure block is set in the MPCBB. |
| SRWILADIS | secure read/write illegal access disable This bit disables the detection of an illegal access when a secure read/write transaction access a non-secure blocks of the block-based SRAM (secure fetch on non-secure block is always considered illegal). 0 (B_0x0): enabled, secure read/write access not allowed on non-secure SRAM block 1 (B_0x1): disabled, secure read/write access allowed on non-secure SRAM block |