PRIV=B_0x0, SREN=B_0x0, SRLOCK=B_0x0, SEC=B_0x0
GTZC1 TZSC memory 4 sub-region A watermark configuration register
| SREN | Sub-region z enable Note: External memories that are watermark controlled start fully non-secure/unprivileged at reset when TZEN = 0xC3. When TZEN = 0xB4, external memories start fully secure/fully privileged (inverted reset-value). 0 (B_0x0): Sub-region A is disabled. Access control of base region x applies to any access between this sub-region start- and end-addresses. 1 (B_0x1): Sub-region A of region x is enabled. Access control defined in GTZC1_TZSC_MPCWMx_CFGR applies to any access between this sub-region start- and end-addresses, both defined in GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR. |
| SRLOCK | Sub-region A lock This bit, once set, can be cleared only by a system reset. 0 (B_0x0): GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written. 1 (B_0x1): Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored. |
| SEC | Secure sub-region A of base region x This bit is taken into account only if SREN is set. 0 (B_0x0): Only non-secure data accesses are granted to sub-region A of region x. 1 (B_0x1): Only secure data accesses are granted to sub-region A of region x. |
| PRIV | Privileged sub-region A of base region x This bit is taken into account only if SREN is set. 0 (B_0x0): Privileged and unprivileged accesses are granted in sub-region A. 1 (B_0x1): Only privileged accesses are granted in sub-region A of region x. |