CODERR=B_0x0, ANACK=B_0x0, COVR=B_0x0, DNACK=B_0x0, PERR=B_0x0, DERR=B_0x0, DOVR=B_0x0, STALL=B_0x0
I3C status error register
| CODERR | protocol error code/type controller detected an illegally formatted CCC controller detected that transmitted data on the bus is different from expected controller detected a not acknowledged broadcast address (7’hE) controller detected the new controller did not drive bus after controller-role hand-off target detected an invalid broadcast address 7’hE+W target detected a parity error on a CCC code via a parity check (vs T bit) target detected a parity error on a write data via a parity check (vs T bit) target detected a parity error on the assigned address during dynamic address arbitration via a parity check (vs PAR bit) target detected a 7’hE+R missing after Sr during dynamic address arbitration target detected an illegally formatted CCC target detected that transmitted data on the bus is different from expected others: reserved 0 (B_0x0): CE0 error (transaction after sending CCC): 1 (B_0x1): CE1 error (monitoring error): 2 (B_0x2): CE2 error (no response to broadcast address): 3 (B_0x3): CE3 error (failed controller-role hand-off): 8 (B_0x8): TE0 error (invalid broadcast address 7’hE+W): 9 (B_0x9): TE1 error (CCC code): 10 (B_0xA): TE2 error (write data): 11 (B_0xB): TE3 error (assigned address during dynamic address arbitration): 12 (B_0xC): TE4 error (7’hE+R missing after Sr during dynamic address arbitration): 13 (B_0xD): TE5 error (transaction after detecting CCC): 14 (B_0xE): TE6 error (monitoring error): |
| PERR | protocol error 0 (B_0x0): no detected error 1 (B_0x1): whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0] |
| STALL | SCL stall error (when the I3C is acting as target) 0 (B_0x0): no detected error 1 (B_0x1): target detected that SCL was stable for more than 125 s during a I3C SDR read |
| DOVR | RX-FIFO overrun or TX-FIFO underrun i) a TX-FIFO underrun: TX-FIFO is empty and a write data byte has to be transmitted ii) a RX-FIFO overrun: RX-FIFO is full and a new data byte is received 0 (B_0x0): no detected error 1 (B_0x1): whatever controller or target, hardware detected either: |
| COVR | C-FIFO underrun or S-FIFO overrun (when the I3C is acting as controller) i) a C-FIFO underrun: control FIFO is empty and a restart has to be emitted ii) a S-FIFO overrun: S-FIFO is full and a new message ends 0 (B_0x0): no detected error 1 (B_0x1): controller detected either: |
| ANACK | address not acknowledged (when the I3C is configured as controller) i) a legacy I2C read/write transfer ii) a direct CCC write transfer iii) the second trial of a direct CCC read transfer iv) a private read/write transfer 0 (B_0x0): no detected error 1 (B_0x1): controller detected that the static/dynamic address was not acknowledged by a target, either during: |
| DNACK | data not acknowledged (when the I3C is acting as controller) i) a legacy I2C write transfer ii) the second trial when sending dynamic address during ENTDAA procedure 0 (B_0x0): no detected error 1 (B_0x1): controller detected that a data byte is not acknowledged by a target, either during: |
| DERR | data error (when the I3C is acting as controller) 0 (B_0x0): no detected error 1 (B_0x1): controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role. |