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stm32 /stm32h5 /STM32H563 /OCTOSPI /OCTOSPI_WTCR

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Interpret as OCTOSPI_WTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCYC

Description

OCTOSPI write timing configuration register

Fields

DCYC

Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended to have at least 5 dummy cycles when using memories with DQS activated.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32