Regviz

stm32 /stm32h5 /STM32H563 /PWR /PWR_IORETR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PWR_IORETR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H562/PWR/PWR_IORETR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IORETEN 0 (B_0x0)JTAGIORETEN

JTAGIORETEN=B_0x0, IORETEN=B_0x0

Description

PWR I/O retention register

Fields

IORETEN

IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register.

0 (B_0x0): IO Retention mode is disable.

1 (B_0x1): IO Retention mode is enabling for all IO except the IO support the standby functionality and PA13, PA14, PA15 and PB4.
JTAGIORETEN

IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode

0 (B_0x0): IO Retention mode is disable.

1 (B_0x1): IO Retention mode is enabling for PA13, PA14, PA15 and PB4.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32