UART12LPEN=B_0x0, FDCAN12LPEN=B_0x0, LPTIM2LPEN=B_0x0, UART9LPEN=B_0x0, UCPDLPEN=B_0x0, DTSLPEN=B_0x0
RCC APB1 sleep clock register
| UART9LPEN | UART9 clock enable during sleep mode Set and reset by software. 0 (B_0x0): UART9 peripheral clock disabled during sleep mode 1 (B_0x1): resets UART9 peripheral clock enabled during sleep mode (default after reset) |
| UART12LPEN | UART12 clock enable during sleep mode Set and reset by software. 0 (B_0x0): UART12 peripheral clock disabled during sleep mode 1 (B_0x1): UART12 peripheral clock enabled during sleep mode (default after reset) |
| DTSLPEN | DTS clock enable during sleep mode Set and reset by software. 0 (B_0x0): DTS peripheral clock disabled during sleep mode 1 (B_0x1): DTS peripheral clock enabled during sleep mode (default after reset) |
| LPTIM2LPEN | LPTIM2 clock enable during sleep mode Set and reset by software. 0 (B_0x0): LPTIM2 peripheral clock disabled during sleep mode 1 (B_0x1): LPTIM2 peripheral clock enabled during sleep mode (default after reset) |
| FDCAN12LPEN | FDCAN1 and FDCAN2 peripheral clock enable during sleep mode Set and reset by software. 0 (B_0x0): FDCAN1 and FDCAN2 peripheral clock disabled during sleep mode 1 (B_0x1): FDCAN1 and FDCAN2 peripheral clock enabled during sleep mode (default after reset) |
| UCPDLPEN | UCPD clock enable during sleep mode Set and reset by software. 0 (B_0x0): UCPD peripheral clock disabled during sleep mode 1 (B_0x1): UCPD peripheral clock enabled during sleep mode (default after reset) |