stm32 /stm32h5 /STM32H563 /RCC /RCC_APB2ENR

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Interpret as RCC_APB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1EN 0 (B_0x0)SPI1EN 0 (B_0x0)TIM8EN 0 (B_0x0)USART1EN 0 (B_0x0)TIM15EN 0 (B_0x0)TIM16EN 0 (B_0x0)TIM17EN 0 (B_0x0)SPI4EN 0 (B_0x0)SPI6EN 0 (B_0x0)SAI1EN 0 (B_0x0)SAI2EN 0 (B_0x0)USBFSEN

USBFSEN=B_0x0, SAI2EN=B_0x0, TIM8EN=B_0x0, TIM16EN=B_0x0, SPI4EN=B_0x0, USART1EN=B_0x0, SPI1EN=B_0x0, TIM1EN=B_0x0, TIM15EN=B_0x0, TIM17EN=B_0x0, SAI1EN=B_0x0, SPI6EN=B_0x0

Description

RCC APB2 peripheral clock register

Fields

TIM1EN

TIM1 clock enable Set and reset by software.

0 (B_0x0): TIM1 peripheral clock disabled (default after reset)

1 (B_0x1): TIM1 peripheral clock enabled

SPI1EN

SPI1 clock enable Set and reset by software.

0 (B_0x0): SPI1 peripheral clock disabled (default after reset)

1 (B_0x1): SPI1 peripheral clock enabled

TIM8EN

TIM8 clock enable Set and reset by software.

0 (B_0x0): TIM8 peripheral clock disabled (default after reset)

1 (B_0x1): TIM8 peripheral clock enabled

USART1EN

USART1 clock enable Set and reset by software.

0 (B_0x0): USART1 peripheral clock disabled (default after reset)

1 (B_0x1): USART1 peripheral clock enabled

TIM15EN

TIM15 clock enable Set and reset by software.

0 (B_0x0): TIM15 peripheral clock disabled (default after reset)

1 (B_0x1): TIM15 peripheral clock enabled

TIM16EN

TIM16 clock enable Set and reset by software.

0 (B_0x0): TIM16 peripheral clock disabled (default after reset)

1 (B_0x1): TIM16 peripheral clock enabled

TIM17EN

TIM17 clock enable Set and reset by software.

0 (B_0x0): TIM17 peripheral clock disabled (default after reset)

1 (B_0x1): TIM17 peripheral clock enabled

SPI4EN

SPI4 clock enable Set and reset by software.

0 (B_0x0): SPI4 peripheral clock disabled (default after reset)

1 (B_0x1): SPI4 peripheral clock enabled

SPI6EN

SPI6 clock enable Set and reset by software.

0 (B_0x0): SPI6 peripheral clock disabled (default after reset)

1 (B_0x1): SPI6 peripheral clock enabled

SAI1EN

SAI1 clock enable Set and reset by software.

0 (B_0x0): SAI1 peripheral clock disabled (default after reset)

1 (B_0x1): SAI1 peripheral clock enabled

SAI2EN

SAI2 clock enable Set and cleared by software.

0 (B_0x0): OCTOSPI1 clock disabled

1 (B_0x1): OCTOSPI1 clock enabled

USBFSEN

USBFS clock enable Set and reset by software.

0 (B_0x0): USBFS peripheral clock disabled (default after reset)

1 (B_0x1): USBFS peripheral clock enabled

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