PLL2REN=B_0x0, PLL2FRACEN=B_0x0, DIVM2=B_0x0, PLL2PEN=B_0x0, PLL2VCOSEL=B_0x0, PLL2QEN=B_0x0, PLL2RGE=B_0x0, PLL2SRC=B_0x0
RCC PLL clock source selection register
| PLL2SRC | DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL2SRC must be set to ‘00’. 0 (B_0x0): no clock send to DIVMx divider and PLLs (default after reset) 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL2RGE | PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2. 0 (B_0x0): PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz |
| PLL2FRACEN | PLL2 fractional latch enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled. 0 (B_0x0): pll2_p_ck output disabled (default after reset) 1 (B_0x1): pll2_p_ck output enabled |
| PLL2VCOSEL | PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2. 0 (B_0x0): wide VCO range 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| DIVM2 | prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1 or PLL2RDY = 1). In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0. … … 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL2PEN | PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, when the pll2_p_ck output of the PLL2 is not used, the pll2_p_ck must be disabled. 0 (B_0x0): pll2_p_ck output disabled (default after reset) 1 (B_0x1): pll2_p_ck output enabled |
| PLL2QEN | PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, when the pll2_q_ck output of the PLL2 is not used, the pll2_q_ck must be disabled. 0 (B_0x0): pll2_q_ck output disabled (default after reset) 1 (B_0x1): pll2_q_ck output enabled |
| PLL2REN | PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, DIVR2EN and DIVR2 bits must be set to 0 when the pll2_r_ck is not used. 0 (B_0x0): pll2_r_ck output disabled (default after reset) 1 (B_0x1): pll2_r_ck output enabled |