PLL3REN=B_0x0, PLL3VCOSEL=B_0x0, PLL3PEN=B_0x0, DIVM3=B_0x0, PLL3QEN=B_0x0, PLL3RGE=B_0x0, PLL3SRC=B_0x0
RCC PLL clock source selection register
| PLL3SRC | DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL3SRC must be set to ‘00’. 0 (B_0x0): no clock send to DIVMx divider and PLLs (default after reset) 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL3RGE | PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. This bit must be written before enabling the PLL3. 0 (B_0x0): PLL3 input (ref3_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL3 input (ref3_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz |
| PLL3FRACEN | PLL3 fractional latch enable Set and reset by software to latch the content of FRACN3 into the sigma-delta modulator. In order to latch the FRACN3 value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN3 into the modulator. |
| PLL3VCOSEL | PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3. 0 (B_0x0): wide VCO range 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| DIVM3 | prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1 or PLL3RDY = 1). In order to save power when PLL3 is not used, the value of DIVM2 must be set to 0. … … 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL3PEN | PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, when the pll3_p_ck output of the PLL3 is not used, the pll3_p_ck must be disabled. 0 (B_0x0): pll3_p_ck output disabled (default after reset) 1 (B_0x1): pll3_p_ck output enabled |
| PLL3QEN | PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, when the pll3_q_ck output of the PLL3 is not used, the pll3_q_ck must be disabled. 0 (B_0x0): pll3_q_ck output disabled (default after reset) 1 (B_0x1): pll3_q_ck output enabled |
| PLL3REN | PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, DIVR2EN and DIVR2 bits must be set to 0 when the pll3_r_ck is not used. 0 (B_0x0): pll3_r_ck output disabled (default after reset) 1 (B_0x1): pll3_r_ck output enabled |