PINRSTF=B_0x0, WWDGRSTF=B_0x0, RMVF=B_0x0, LPWRRSTF=B_0x0, BORRSTF=B_0x0, IWDGRSTF=B_0x0, SFTRSTF=B_0x0
RCC reset status register
| RMVF | remove reset flag Set and reset by software to reset the value of the reset flags. 0 (B_0x0): reset of the reset flags not activated (default after power-on reset) 1 (B_0x1): resets the value of the reset flags |
| PINRSTF | pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. 0 (B_0x0): no reset from pin occurred 1 (B_0x1): reset from pin occurred (default after power-on reset) |
| BORRSTF | BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). 0 (B_0x0): no BOR reset occurred 1 (B_0x1): BOR reset occurred (default after power-on reset) |
| SFTRSTF | system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33. 0 (B_0x0): no CPU software reset occurred (default after power-on reset) 1 (B_0x1): a system reset has been generated by the CPU |
| IWDGRSTF | independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. 0 (B_0x0): no independent watchdog reset occurred (default after power-on reset) 1 (B_0x1): independent watchdog reset occurred |
| WWDGRSTF | window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. 0 (B_0x0): no window watchdog reset occurred from WWDG (default after power-on reset) 1 (B_0x1): window watchdog reset occurred from WWDG |
| LPWRRSTF | Low-power reset flag Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared. Cleared by writing to the RMVF bit. 0 (B_0x0): No illegal low-power mode reset occurred 1 (B_0x1): Illegal low-power mode reset occurred |