OSR=B_0x0, DMAEN=B_0x0, PRTCFG=B_0x0, MODE=B_0x0, MCKDIV=B_0x0, SYNCEN=B_0x0, NODIV=B_0x0, MONO=B_0x0, OUTDRIV=B_0x0, LSBFIRST=B_0x0, CKSTR=B_0x0, MCKEN=B_0x0, SAIEN=B_0x0
SAI configuration register 1
| MODE | SAIx audio block mode These bits are set and cleared by software. They must be configured when SAIx audio block is disabled. Note: When the audio block is configured in SPDIF mode, the master transmitter mode is forced (MODE[1:0] = 00). 0 (B_0x0): Master transmitter 1 (B_0x1): Master receiver 2 (B_0x2): Slave transmitter 3 (B_0x3): Slave receiver |
| PRTCFG | Protocol configuration These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 0 (B_0x0): Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol (such as I2S, LSB/MSB justified, TDM, PCM/DSP…) by setting most of the configuration register bits as well as frame configuration register. 1 (B_0x1): SPDIF protocol 2 (B_0x2): AC’97 protocol |
| DS | Data size These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 2 (B_0x2): 8 bits 3 (B_0x3): 10 bits 4 (B_0x4): 16 bits 5 (B_0x5): 20 bits 6 (B_0x6): 24 bits 7 (B_0x7): 32 bits |
| LSBFIRST | Least significant bit first This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC’97 audio protocol since AC’97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 0 (B_0x0): Data are transferred with MSB first 1 (B_0x1): Data are transferred with LSB first |
| CKSTR | Clock strobing edge This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 0 (B_0x0): Signals generated by the SAI change on SCK rising edge, while signals received by the SAI are sampled on the SCK falling edge. 1 (B_0x1): Signals generated by the SAI change on SCK falling edge, while signals received by the SAI are sampled on the SCK rising edge. |
| SYNCEN | Synchronization enable These bits are set and cleared by software. They must be configured when the audio subblock is disabled. Note: The audio subblock should be configured as asynchronous when SPDIF mode is enabled. 0 (B_0x0): audio subblock in asynchronous mode. 1 (B_0x1): audio subblock is synchronous with the other internal audio subblock. In this case, the audio subblock must be configured in slave mode 2 (B_0x2): audio subblock is synchronous with an external SAI embedded peripheral. In this case the audio subblock should be configured in Slave mode. |
| MONO | Mono mode This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to for more details. 0 (B_0x0): Stereo mode 1 (B_0x1): Mono mode. |
| OUTDRIV | Output drive This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 0 (B_0x0): Audio block output driven when SAIEN is set 1 (B_0x1): Audio block output driven immediately after the setting of this bit. |
| SAIEN | Audio block enable This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command is not taken into account. This bit allows controlling the state of the SAI audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When the SAI block (A or B) is configured in master mode, the clock must be present on the SAI block input before setting SAIEN bit. 0 (B_0x0): SAI audio block disabled 1 (B_0x1): SAI audio block enabled. |
| DMAEN | DMA enable This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 0 (B_0x0): DMA disabled 1 (B_0x1): DMA enabled |
| NODIV | No divider This bit is set and cleared by software. 0 (B_0x0): the ratio between the Master clock generator and frame synchronization is fixed to 256 or 512 1 (B_0x1): the ratio between the Master clock generator and frame synchronization depends on FRL[7:0] |
| MCKDIV | Master clock divider These bits are set and cleared by software. Otherwise, The master clock frequency is calculated according to the formula given in . These bits have no meaning when the audio block is slave. They have to be configured when the audio block is disabled. 0 (B_0x0): Divides by 1 the kernel clock input (sai_x_ker_ck). |
| OSR | Oversampling ratio for master clock This bit is meaningful only when NODIV bit is set to 0. 0 (B_0x0): Master clock frequency = FFS x 256 1 (B_0x1): Master clock frequency = FFS x 512 |
| MCKEN | Master clock generation enable 0 (B_0x0): The master clock is not generated 1 (B_0x1): The master clock is generated independently of SAIEN bit |