COMP=B_0x0, MUTEVAL=B_0x0, CPL=B_0x0, TRIS=B_0x0, MUTE=B_0x0, FTH=B_0x0, FFLUSH=B_0x0
SAI configuration register 2
| FTH | FIFO threshold. This bit is set and cleared by software. 0 (B_0x0): FIFO empty 1 (B_0x1): FIFO 2 (B_0x2): FIFO 3 (B_0x3): FIFO 4 (B_0x4): FIFO full |
| FFLUSH | FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 0 (B_0x0): No FIFO flush. 1 (B_0x1): FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled |
| TRIS | Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to for more details. 0 (B_0x0): SD output line is still driven by the SAI when a slot is inactive. 1 (B_0x1): SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive. |
| MUTE | Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 0 (B_0x0): No mute mode. 1 (B_0x1): Mute mode enabled. |
| MUTEVAL | Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 0 (B_0x0): Bit value 0 is sent during the mute mode. 1 (B_0x1): Last values are sent during the mute mode. |
| MUTECNT | Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET is set and an interrupt is generated if bit MUTEDETIE is set. Refer to for more details. |
| CPL | Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 0 (B_0x0): 1’s complement representation. 1 (B_0x1): 2’s complement representation. |
| COMP | Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that is used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to for more details. Note: Companding mode is applicable only when Free protocol mode is selected. 0 (B_0x0): No companding algorithm 2 (B_0x2): -Law algorithm 3 (B_0x3): A-Law algorithm |