RDY2=B_0x0, CS2=B_0x0, RDY1=B_0x0, CS1=B_0x0, EN1=B_0x0, EN2=B_0x0
SBS compensation cell for I/Os control and status register
| EN1 | enable compensation cell for VDDIO power rail This bit enables the I/O compensation cell. 0 (B_0x0): I/O compensation cell disabled 1 (B_0x1): I/O compensation cell enabled |
| CS1 | code selection for VDDIO power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. 0 (B_0x0): Code from the cell (available in the SBS_CCVR) 1 (B_0x1): Code from SBS_CCCR |
| EN2 | enable compensation cell for VDDIO2 power rail This bit enables the I/O compensation cell. 0 (B_0x0): I/O compensation cell disabled 1 (B_0x1): I/O compensation cell enabled |
| CS2 | code selection for VDDIO2 power rail (reset value set to 1) This bit selects the code to be applied for the I/O compensation cell. 0 (B_0x0): Code from the cell (available in SBS_CCVR) 1 (B_0x1): Code from SBS_CCCR |
| RDY1 | VDDIO compensation cell ready flag This bit provides the status of the compensation cell. 0 (B_0x0): VDDIO compensation cell not ready 1 (B_0x1): VDDIO compensation cell ready (code value provided by the cell can be used) |
| RDY2 | VDDIO2 compensation cell ready flag This bit provides the status of the VDDIO2 compensation cell. 0 (B_0x0): VDDIO2 compensation cell not ready 1 (B_0x1): VDDIO2 compensation cell ready (code value provided by the cell can be used) |