SEL=B_0x0, ECCL=B_0x0, PVDL=B_0x0, CLL=B_0x0
SBS Class B register
| CLL | core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs. 0 (B_0x0): lockup output disconnected from timer break inputs 1 (B_0x1): lockup output connected to timer break inputs |
| SEL | SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17. 0 (B_0x0): SRAM double ECC error flag disconnected from timer break inputs 1 (B_0x1): SRAM double ECC error flag connected to timer break inputs |
| PVDL | PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs. 0 (B_0x0): PVD interrupt disconnected from timer break inputs. PVD_EN and PVD_SEL[2:0] in the PWR registers are read/write. 1 (B_0x1): PVD interrupt is connected to timer break inputs. PVD_EN and PVD_SEL[2:0] in the PWR registers are read only |
| ECCL | ECC lock This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17. 0 (B_0x0): double ECC error flag disconnected to timer break inputs 1 (B_0x1): double ECC error flag connected to timer break inputs |