LOCKSMPU=B_0x0, LOCKSVTAIRCR=B_0x0, LOCKSAU=B_0x0
SBS CPU secure lock register
| LOCKSVTAIRCR | VTOR_S and AIRCR register lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register. 0 (B_0x0): VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write enabled 1 (B_0x1): VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write disabled |
| LOCKSMPU | secure MPU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers. 0 (B_0x0): Secure MPU registers writes enabled 1 (B_0x1): Secure MPU registers writes disabled |
| LOCKSAU | SAU registers lock This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers. 0 (B_0x0): SAU registers write enabled 1 (B_0x1): SAU registers write disabled |