Regviz

stm32 /stm32h5 /STM32H563 /SBS /SBS_FPUIMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SBS_FPUIMR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H503/SBS/SBS_FPUIMR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FPU_IE

Description

SBS FPU interrupt mask register

Fields

FPU_IE

FPU interrupt enable Set and cleared by software to enable the Cortex-M33 FPU interrupts FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset) FPU_IE[4]: input abnormal interrupt enable FPU_IE[3]: overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: divide-by-zero interrupt enable FPU_IE[0]: invalid operation interrupt enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32