CLASSBSEC=B_0x0, SDCE_SEC_EN=B_0x0, FPUSEC=B_0x0, SBSSEC=B_0x0
SBS security mode configuration control register
| SBSSEC | SBS clock control, memory-erase status register and compensation cell register security enable 0 (B_0x0): SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible through secure or non-secure transaction 1 (B_0x1): SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers only accessible through secure transaction |
| CLASSBSEC | ClassB security enable 0 (B_0x0): SBS_CFGR2 register accessible through secure or non-secure transaction 1 (B_0x1): SBS_CFGR2 register only accessible through secure transaction |
| FPUSEC | FPU security enable Note: This bit can only be written through privilege transaction. 0 (B_0x0): SBS_FPUIMP register accessible through secure or non-secure transaction 1 (B_0x1): SBS_FPUIMP register only accessible through secure transaction |
| SDCE_SEC_EN | control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR 0 (B_0x0): SMPS_DIV_CLOCK _EN accessible through a secure or non-secure transaction 1 (B_0x1): SMPS_DIV_CLOCK _EN only accessible through a secure transaction |