TG=B_0x0, BG=B_0x0, UG=B_0x0, COMG=B_0x0, CC1G=B_0x0
TIM15 event generation register
| UG | Update generation This bit can be set by software, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). |
| CC1G | Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 1 A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIM15_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 0 (B_0x0): No action |
| CC2G | Capture/Compare 2 generation Refer to CC1G description |
| COMG | Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): No action 1 (B_0x1): When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits |
| TG | Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): The TIF flag is set in TIM15_SR register. Related interrupt or DMA transfer can occur if enabled |
| BG | Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. |