DORSTAT2=B_0x0, CAL_FLAG2=B_0x0, BWST1=B_0x0, CAL_FLAG1=B_0x0, DAC2RDY=B_0x0, DMAUDR2=B_0x0, DMAUDR1=B_0x0, DORSTAT1=B_0x0, BWST2=B_0x0, DAC1RDY=B_0x0
DAC status register
| DAC1RDY | DAC channel1 ready status bit This bit is set and cleared by hardware. 0 (B_0x0): DAC channel1 is not yet ready to accept the trigger nor output data 1 (B_0x1): DAC channel1 is ready to accept the trigger or output data |
| DORSTAT1 | DAC channel1 output register status bit This bit is set and cleared by hardware. It is applicable only when the DAC operates in Double data mode. 0 (B_0x0): DOR[11:0] is used actual DAC output 1 (B_0x1): DORB[11:0] is used actual DAC output |
| DMAUDR1 | DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0 (B_0x0): No DMA underrun error condition occurred for DAC channel1 1 (B_0x1): DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) |
| CAL_FLAG1 | DAC channel1 calibration offset status This bit is set and cleared by hardware 0 (B_0x0): calibration trimming value is lower than the offset correction value 1 (B_0x1): calibration trimming value is equal or greater than the offset correction value |
| BWST1 | DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI/LSE periods of synchronization). 0 (B_0x0): There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written 1 (B_0x1): There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written |
| DAC2RDY | DAC channel2 ready status bit This bit is set and cleared by hardware. Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): DAC channel2 is not yet ready to accept the trigger nor output data 1 (B_0x1): DAC channel2 is ready to accept the trigger or output data |
| DORSTAT2 | DAC channel2 output register status bit This bit is set and cleared by hardware. It is applicable only when the DAC operates in Double data mode. Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): DOR[11:0] is used actual DAC output 1 (B_0x1): DORB[11:0] is used actual DAC output |
| DMAUDR2 | DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): No DMA underrun error condition occurred for DAC channel2 1 (B_0x1): DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate). |
| CAL_FLAG2 | DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): calibration trimming value is lower than the offset correction value 1 (B_0x1): calibration trimming value is equal or greater than the offset correction value |
| BWST2 | DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI/LSE periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation. 0 (B_0x0): There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written 1 (B_0x1): There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written |