stm32 /stm32h5 /STM32H573 /DCACHE /DCACHE_CMDREADDRR

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Interpret as DCACHE_CMDREADDRR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CMDENDADDR

Description

DCACHE command range end address register

Fields

CMDENDADDR

end address of range to which the cache maintenance command specified in DCACHE_CR.CACHECMD field applies This register must be set before DCACHE_CR.CACHECMD is written.

Links

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