FRAME_IE=B_0x0, ERR_IE=B_0x0, VSYNC_IE=B_0x0, OVR_IE=B_0x0, LINE_IE=B_0x0
DCMI interrupt enable register
| FRAME_IE | Capture complete interrupt enable 0 (B_0x0): No interrupt generation 1 (B_0x1): An interrupt is generated at the end of each received frame/crop window (in crop mode). |
| OVR_IE | Overrun interrupt enable 0 (B_0x0): No interrupt generation 1 (B_0x1): An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received. |
| ERR_IE | Synchronization error interrupt enable Note: This bit is available only in embedded synchronization mode. 0 (B_0x0): No interrupt generation 1 (B_0x1): An interrupt is generated if the embedded synchronization codes are not received in the correct order. |
| VSYNC_IE | DCMI_VSYNC interrupt enable The active state of the DCMI_VSYNC signal is defined by the VSPOL bit. 0 (B_0x0): No interrupt generation 1 (B_0x1): An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state. |
| LINE_IE | Line interrupt enable 0 (B_0x0): No interrupt generation when the line is received 1 (B_0x1): An Interrupt is generated when a line has been completely received. |