FRAME_MIS=B_0x0, ERR_MIS=B_0x0, LINE_MIS=B_0x0, VSYNC_MIS=B_0x0, OVR_MIS=B_0x0
DCMI masked interrupt status register
| FRAME_MIS | Capture complete masked interrupt status This bit gives the status of the masked capture complete interrupt 0 (B_0x0): No interrupt is generated after a complete capture. 1 (B_0x1): An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER. |
| OVR_MIS | Overrun masked interrupt status This bit gives the status of the masked overflow interrupt. 0 (B_0x0): No interrupt is generated on overrun. 1 (B_0x1): An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER. |
| ERR_MIS | Synchronization error masked interrupt status This bit gives the status of the masked synchronization error interrupt. Note: This bit is available only in embedded synchronization mode. 0 (B_0x0): No interrupt is generated on a synchronization error. 1 (B_0x1): An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set. |
| VSYNC_MIS | VSYNC masked interrupt status This bit gives the status of the masked VSYNC interrupt. The active state of the DCMI_VSYNC signal is defined by the VSPOL bit. 0 (B_0x0): No interrupt is generated on DCMI_VSYNC transitions. 1 (B_0x1): An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER. |
| LINE_MIS | Line masked interrupt status This bit gives the status of the masked line interrupt. 0 (B_0x0): No interrupt generation when the line is received 1 (B_0x1): An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER. |