stm32 /stm32h5 /STM32H573 /ETH /ETH_DMAMR

Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all clock domains. Before reprogramming any register, a value of zero should be read in this bit. Note: The reset operation is complete only when all resets in all active clock domains are deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock.

DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. The Tx path has priority over the Rx path when the TXPR bit is set. Otherwise, the Rx path has priority over the Tx path.

0 (B_0x0): Weighted Round-Robin with Rx:Tx or Tx:Rx

1 (B_0x1): Fixed priority

Transmit priority When set, this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus.

Priority ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set.

0 (B_0x0): The priority ratio is 1:1

1 (B_0x1): The priority ratio is 2:1

2 (B_0x2): The priority ratio is 3:1

3 (B_0x3): The priority ratio is 4:1

4 (B_0x4): The priority ratio is 5:1

5 (B_0x5): The priority ratio is 6:1

6 (B_0x6): The priority ratio is 7:1

7 (B_0x7): The priority ratio is 8:1

Interrupt Mode This field defines the interrupt mode of the Ethernet peripheral. The behavior of the interrupt signal and of the RI/TI bits in the ETH_DMACSR register changes depending on the INTM value (refer to Table651: Transfer complete interrupt behavior).