stm32 /stm32h5 /STM32H573 /ETH /ETH_MACHWF1R

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Interpret as ETH_MACHWF1R

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXFIFOSIZE0 (B_0x0)TXFIFOSIZE0 (OSTEN)OSTEN 0 (PTOEN)PTOEN 0 (ADVTHWORD)ADVTHWORD 0 (B_0x0)ADDR64 0 (DCBEN)DCBEN 0 (SPHEN)SPHEN 0 (TSOEN)TSOEN 0 (DBGMEMA)DBGMEMA 0 (AVSEL)AVSEL 0 (RAVSEL)RAVSEL 0 (POUOST)POUOST 0 (B_0x0)HASHTBLSZ 0 (B_0x0)L3L4FNUM

RXFIFOSIZE=B_0x0, HASHTBLSZ=B_0x0, ADDR64=B_0x0, TXFIFOSIZE=B_0x0, L3L4FNUM=B_0x0

Description

HW feature 1 register

Fields

RXFIFOSIZE

MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7: 01100 to 11111: Reserved, must not be used

0 (B_0x0): 128 bytes

1 (B_0x1): 256 bytes

2 (B_0x2): 512 bytes

3 (B_0x3): 1,024 bytes

4 (B_0x4): 2,048 bytes

5 (B_0x5): 4,096 bytes

6 (B_0x6): 8,192 bytes

7 (B_0x7): 16,384 bytes

8 (B_0x8): 32 Kbytes

9 (B_0x9): 64 Kbytes

10 (B_0xA): 128 Kbytes

11 (B_0xB): 256 Kbytes

TXFIFOSIZE

MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7: 01011 to 11111: Reserved, must not be used

0 (B_0x0): 128 bytes

1 (B_0x1): 256 bytes

2 (B_0x2): 512 bytes

3 (B_0x3): 1,024 bytes

4 (B_0x4): 2,048 bytes

5 (B_0x5): 4,096 bytes

6 (B_0x6): 8,192 bytes

7 (B_0x7): 16,384 bytes

8 (B_0x8): 32 Kbytes

9 (B_0x9): 64 Kbytes

10 (B_0xA): 128 Kbytes

OSTEN

One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.

PTOEN

PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.

ADVTHWORD

IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected

ADDR64

Address width This field indicates the configured address width. Others: Reserved, must not be used

0 (B_0x0): 32 bits

DCBEN

DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected

SPHEN

Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected

TSOEN

TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected

DBGMEMA

DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected

AVSEL

AV Feature Enable This bit is set to 1 when the Enable Audio video bridging option is selected.

RAVSEL

Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio video bridging option on Rx Side Only is selected.

POUOST

One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable one step timestamp for PTP over UDP/IP feature is selected.

HASHTBLSZ

Hash Table Size This field indicates the size of the Hash table:

0 (B_0x0): No Hash table

1 (B_0x1): 64

2 (B_0x2): 128

3 (B_0x3): 256

L3L4FNUM

Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: …

0 (B_0x0): No L3 or L4 Filter

1 (B_0x1): 1 L3 or L4 Filter

2 (B_0x2): 2 L3 or L4 Filters

8 (B_0x8): 8 L3 or L4

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