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stm32 /stm32h5 /STM32H573 /ETH /ETH_MTLISR

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Interpret as ETH_MTLISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Q0IS)Q0IS

Description

Interrupt status Register

Fields

Q0IS

Queue interrupt status This bit indicates that an interrupt has been generated by Queue. To reset this bit, read ETH_MTLQICSR register to identify the interrupt cause and clear the source.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32