ECCCIE=B_0x0
FLASH ECC correction register
| ADDR_ECC | ECC error address When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). |
| OBK_ECC | Single ECC error corrected in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. |
| EDATA_ECC | ECC fail for corrected ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. |
| BK_ECC | ECC fail bank for corrected ECC error It indicates which bank is concerned by ECC error |
| SYSF_ECC | ECC fail for corrected ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. |
| OTP_ECC | OTP ECC error bit This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. |
| ECCCIE | ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation. 0 (B_0x0): no interrupt generated when an ECC single correction error occurs 1 (B_0x1): non-secure interrupt generated when an ECC single correction error occurs |
| ECCC | ECC correction set by hardware when single ECC error has been detected and corrected. Cleared by writing 1. |