FLASH ECC detection register
| ADDR_ECC | ECC error address When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error. ADDR_ECC is reset when the flag error is reset. The flash interface programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved. The address in ADDR_ECC is relative to the flash memory area where the error occurred (user flash memory, system flash memory, data area, read-only/OTP area). |
| OBK_ECC | ECC fail double ECC error in flash OB Keys storage area. It indicates the OBK storage concerned by ECC error. |
| EDATA_ECC | ECC fail double ECC error in flash high-cycle data area It indicates if flash high-cycle data area is concerned by ECC error. |
| BK_ECC | ECC fail bank for double ECC error It indicates which bank is concerned by ECC error |
| SYSF_ECC | ECC fail for double ECC error in system flash memory It indicates if system flash memory is concerned by ECC error. |
| OTP_ECC | OTP ECC error bit This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield. |
| ECCD | ECC detection Set by hardware when two ECC error has been detected. When this bit is set, a NMI is generated. Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors. |