stm32 /stm32h5 /STM32H573 /FLASH /FLASH_NSCR

configuration lock bit This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset. LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change.

0 (B_0x0): FLASH_NSCR register unlocked

1 (B_0x1): FLASH_NSCR register locked

programming control bit PG can be programmed only when LOCK is cleared to 0. PG allows programming in Bank1 and Bank2.

0 (B_0x0): programming disabled

1 (B_0x1): programming enabled

sector erase request Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised.

0 (B_0x0): sector erase not requested

1 (B_0x1): sector erase requested

erase request Setting BER bit to 1 requests a bank erase operation (user flash memory only). BER can be programmed only when LOCK is cleared to 0. If MER and SER are also set, a PGSERR is raised. Note: Write protection error is triggered when a bank erase is required and some sectors are protected.

0 (B_0x0): bank erase not requested

1 (B_0x1): bank erase requested

write forcing control bit FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0. The embedded flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error. Write forcing is effective only if the write buffer is not empty and was filled by non-secure access (in particular, FW does not start several write operations when the force-write operations are performed consecutively). Since there is just one write buffer, FW can force a write in bank1 or bank2.

erase start control bit STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0. STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software.

sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0. …

0 (B_0x00): Sector 0 selected

1 (B_0x01): Sector 1 selected

127 (B_0x7F): Sector 127 selected

Mass erase request Setting MER bit to 1 requests a mass erase operation (user flash memory only). MER can be programmed only when LOCK is cleared to 0. If BER or SER are both set, a PGSERR is raised. Error is triggered when a mass erase is required and some sectors are protected.

0 (B_0x0): mass erase not requested

1 (B_0x1): mass erase requested

end of operation interrupt control bit Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0.

0 (B_0x0): no interrupt generated at the end of operation.

1 (B_0x1): interrupt enabled when at the end of operation

write protection error interrupt enable bit When this bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0.

0 (B_0x0): no interrupt generated when a protection error occurs

1 (B_0x1): interrupt generated when a protection error occurs

programming sequence error interrupt enable bit When this bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0.

0 (B_0x0): no interrupt generated when a sequence error occurs

1 (B_0x1): interrupt generated when sequence error occurs

strobe error interrupt enable bit When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0.

0 (B_0x0): no interrupt generated when a strobe error occurs

1 (B_0x1): interrupt generated when strobe error occurs.

inconsistency error interrupt enable bit When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0.

0 (B_0x0): no interrupt generated when a inconsistency error occurs

1 (B_0x1): interrupt generated when a inconsistency error occurs.

OBK general error interrupt enable bit OBKERRIE enables generating an interrupt in case of OBK specific access error. This bit can be programmed only when LOCK bit is cleared to 0.

0 (B_0x0): no interrupt is generated on OBK general access error

1 (B_0x1): an interrupt is generated on OBK general access error

OBK write error interrupt enable bit OBKWERRIE enables generation of interrupt in case of OBK specific write error. This bit can be programmed only when LOCK bit is cleared to 0.

0 (B_0x0): no interrupt is generated on OBK write error

1 (B_0x1): an interrupt is generated on OBK write error

Option byte change error interrupt enable bit This bit controls if an interrupt must be generated when an error occurs during an option byte change. It can be programmed only when LOCK bit is cleared to 0.

0 (B_0x0): no interrupt is generated when an error occurs during an option byte change

1 (B_0x1): an interrupt is generated when and error occurs during an option byte change.

Bank selector bit BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored.

0 (B_0x0): Bank1 is selected for Bank erase / sector erase / interrupt enable

1 (B_0x1): Bank2 is selected for BER / SER