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stm32 /stm32h5 /STM32H573 /FMC /FMC_SDSR

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Interpret as FMC_SDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RE 0 (B_0x0)MODES1 0 (B_0x0)MODES2 0 (B_0x0)BUSY

RE=B_0x0, MODES2=B_0x0, BUSY=B_0x0, MODES1=B_0x0

Description

SDRAM status register

Fields

RE

Refresh error flag An interrupt is generated if REIE = 1 and RE = 1

0 (B_0x0): No refresh error has been detected

1 (B_0x1): A refresh error has been detected
MODES1

Status Mode for Bank 1 This bit defines the Status Mode of SDRAM Bank 1.

0 (B_0x0): Normal Mode

1 (B_0x1): Self-refresh mode

2 (B_0x2): Power-down mode
MODES2

Status Mode for Bank 2 This bit defines the Status Mode of SDRAM Bank 2.

0 (B_0x0): Normal Mode

1 (B_0x1): Self-refresh mode

2 (B_0x2): Power-down mode
BUSY

Busy status This bit defines the status of the SDRAM controller after a Command Mode request 1; SDRAM Controller is not ready to accept a new request

0 (B_0x0): SDRAM Controller is ready to accept a new request

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32